1. Field of the Invention
The present invention is directed to a process of removing holefill residue from a metallic or dielectric surface of an electronic substrate. More specifically, the present invention is directed to a process for removing holefill residue from a metallic or dielectric surface of an electronic substrate by exposing the residue to a swelling agent followed by planarizing.
2. Background of the Prior Art
Printed wiring boards (PWBs), such as printed circuit boards, chip carriers or multichip modules, are well known examples of electronic substrates. PWBs usually comprise layers of conductive and dielectric materials laminated together. Some of the layers include conductors or signal lines, prepared by methods well known in the art, on a dielectric layer and other layers may comprise a sheet of metal laminated, plated or evaporated onto the dielectric layer to serve as a ground or power plane. Typically, a surface layer includes printed conductors, metallic pads and components mounted to the pads. The components may include resistors, capacitors, amplifiers, processor chips, memory chips, application specific integrated circuits, optical devices and the like. Also, such components could be any of the foregoing electronic devices mounted on a carrier, the carrier being mounted onto the PWB. Some of the printed conductors on the surface layer connect to pads and thereby participate in electrically connecting the respective components to other components, power and ground. However, because of surface area limitations, the surface layer may not be able to accommodate all the printed conductors that are required. Therefore, plated through holes (PTHs) and blind vias are also provided by drilling, punching or ablating in the PWB and subsequent deposition of a conductive material in the hole to interconnect printed conductors on the surface layer to printed conductors or metallic planes on inner layers. Some of these printed conductors are also connected to surface pads to which components are mounted. Thus, the printed conductors and metallic planes on the inner layers also participate in connections to the components on the surface layer.
It is particularly desirable that the PTHs and blind vias ultimately be filled and overplated or capped in order to increase the mechanical strength of the PWB, to provide electrical conductivity over the complete surface of the PWB and, in general, to increase the useable space of the PTH. The resulting structure provides for the option of attaching an electronic component directly over the capped hole, rather than requiring the use of the typical so-called dogbone type connection wherein a component is attached to a conductive pad that is adjacent to a conventional plated through hole and connected with a dogbone connection. Elimination of the need for a dogbone connection results in a significant increase in possible wiring density on the surface of the printed wiring board of the chip carrier. Especially in the case of a chip carrier, where a dense area array of solder interconnections to the chip is required, the ability to directly attach a plurality of the solder interconnections directly above a capped plated through hole or blind via is advantageous.
While improving the possible interconnection density, the use of filled and capped plated through holes have other advantages. The material that fills the holes may have a range of mechanical and electrical properties, depending upon its formulation. In general, the holefill material is a polymer mixture that has various fillers added to tailor its properties. For example, the thermal expansion rate of the material can be reduced by added low expansion particles such as copper particles or silica particles. If a sufficient number of electrically conducting particles are added, then the mixture will be conductive. Conductivity can be achieved when the volume fraction of particles is sufficient to ensure that there is a continuous path through the material. The conductive path may be occur by particle to particle physical contact or it may be occur due to alloying of adjacent particles during the heating process that cures the polymer matrix.
Depending upon the physical and mechanical characteristics of the printed wiring board, a plated through hole is subjected to some thermally induced stress due to the inevitable heating and cooling that occurs in electronic components during their service life. By selecting a holefill material with the correct characteristics, the stresses imparted upon the plated through hole may be diminished, thus improving its reliability. In the event that the holefill material is electrically conductive a greater robustness can be achieved by virtue of the alternate current path that is provided in the event that the metallic plating is thin or becomes defective during its service life.
A further extension of the use of electrically conductive holefill material to augment metallic hole wall plating is the complete elimination of metallic plating and use only of the conductive hole fill material. Such a design provides significant opportunity for cost reduction and simplicity by eliminating the need for plating the sidewalls of the hole and thereby eliminating processing steps. In this process the sidewalls of the holes are not plated prior to filling the holes with a conductive material. The outer surface of the partially completed printed wiring board requires a conductive layer to form individual printed conductors that connect to the conductive holes. This outer conductive surface may be provided either before or after the hole filling process is conducted.
Materials employed in filling PTHs and blind vias are usually organic materials with metallic or inorganic fillers. The filling of PTHs is described in U.S. Pat. No. 5,822,856. Improved methods of filling PTHs and blind vias in PWBs are also set forth in U.S. Pat. No. 6,015,520. In addition, U.S. Pat. No. 6,125,531 discusses methods of making PCBs having filled holes and wherein the holefill is provided with reinforcement means.
There are many methods of filling PTHs and blind vias in electronic substrates such as PWBs. For example, such holes are often filled by utilization of a doctor blade. In this method PTHs and blind vias are filled and smoothed over with the holefill material. Unfortunately, these methods result in residual holefill which overlaps the surface of the PWB. As mentioned above, the surface of the PWB at this step of the fabrication process may be either a dielectric material or a conductive metal. Thus, it is necessary to planarize the overfilled PTHs and blind vias without damaging the outer surface of the PWB. Although polishing of metal surfaces of electronic substrates and, indeed, the planarizing of metal circuitry on PWBs is well known in the art and is excellently accomplished with metal etchants, as taught, for instance, in U.S. Pat. No. 5,759,427, such a method is undesirable in the present application. This is so insofar as the removal of metal, commonly copper, from the surface of a PWB or the like may in some instances be deemed detrimental. For example, a layer of copper, thinner than desired, results in a PWB having adverse electrical properties. Thus, the present method of removing holefill by utilizing mild chemical etching, which removes metal as well as holefill, is undesirable. Therefore, there is a strong need in the art for a new process of removing the excess holefill over PTHs and blind vias on PWBs and other electronic substrates having a metallic or dielectric surface which removes excess holefill and insures a planarized surface without the loss of metal thickness.
A new process for removing holefill residue from a metallic or dielectric surface of an electronic substrate has now been developed. This process planarizes the metallic or dielectric surface of the electronic substrate without any appreciable removal of metal or dielectric material from the metal or dielectric surface.
In accordance with the present invention a process is provided for removing holefill residue from a metallic or dielectric surface of an electronic substrate which comprises the steps of contacting holefill residue on a surface of a metallic or dielectric surface of an electronic substrate with a swelling agent and thereafter mechanically planarizing the surface contacted with the swelling agent.